View HA0041E_4924881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT48RA0-3/HT48CA0-3 Remote Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series - HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series - HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals - HA0075E MCU Reset and Oscillator Circuits Application Note - HA0076E HT48RAx/HT48CAx Software Application Note - HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
* Operating voltage: fSYS=4MHz(3%) at 2.0V~3.6V, * Power-down and wake-up features reduce power
Temperature = 0C ~ +50C
* 10 bidirectional I/O lines * 6 Schmitt trigger input lines
consumption
* 62 powerful instructions * Up to 1ms instruction cycle with 4MHz system clock * All instructions executed in 1 or 2 machine cycles * 14-bit table read instructions * One-level subroutine nesting * Bit manipulation instructions * Low voltage reset function * 20-pin SOP/SSOP package
(PB7 without Pull-high resistor)
* One programmable carrier output - using 9-bit timer * On-chip RC oscillator - 4MHz 3% when
VDD=2.0V~3.6V; Temperature = 0C ~ +50C
* Watchdog Timer * 1K14 program memory * 328 data RAM
General Description
The HT48RA0-3/HT48CA0-3 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. The mask version HT48CA0-3 is fully pin and functionally compatible with the OTP version HT48RA0-3 device. The advantages of low power consumption, I/O flexibility, timer functions, watchdog timer, HALT and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of application possibilities such as industrial control, consumer products, and particularly suitable for use in products such as infrared remote controllers and various subsystem controllers.
Rev.1.10
1
October 12, 2007
HT48RA0-3/HT48CA0-3
Block Diagram
P ro g ra m P ro g ra m C o u n te r STACK fS
YS
/4
In s tr u c tio n R e g is te r
F re q u e n c y D iv id e r MP M U X DATA M e m o ry
W DT
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
C a r r ie r G e n e ra to r 9 - b it T im e r PORT B PB PORT A
REM
STATUS
S h ifte r
PB0~PB1 PB2~PB7 PA0~PA7
OSC1 VDD VSS
ACC
PA
Pin Assignment
PA1 1 2 3 4 5 6 7 8 9 10 PA0 PB1 PB0 REM VSS PB6 OSC1 VDD PB7 20 19 18 17 16 15 14 13 12 11 PA2 PA3 PA4 PA5 PA6 PA7 PB2 PB3 PB4 PB5
H T 4 8 R A 0 -3 /H T 4 8 C A 0 -3 2 0 S O P -A /S S O P -A
Rev.1.10
2
October 12, 2007
HT48RA0-3/HT48CA0-3
Pin Description
Pin Name PA0~PA7 I/O I/O Configuration Option 3/4 Description Bidirectional 8-bit input/output port with pull-high resistors. Software instructions determine if the pin is an NMOS output or Schmitt Trigger input. Bidirectional 2-bit input/output lines with pull-high resistors. Each individual bit can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is an NMOS output or Schmitt Trigger input. 5-bit Schmitt Trigger input lines with pull-high resistors. Each individual bit can be configured as a wake-up input by a configuration option. 1-bit Schmitt trigger input lines without pull-high resistor. This bit can be configured as a wake-up input by a configuration option. Carrier output pin. OSC1 is connected to an external resistor for the internal system clock. Positive power supply Negative power supply, ground
PB0, PB1
I/O
Wake-up
PB2~PB6 PB7 REM OSC1 VDD VSS
I I O I 3/4 3/4
Wake-up Wake-up 3/4 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+4.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol VDD IDD ISTB VIL VIH VLVR IOL IOH RPH VPOR RPOR Parameter VDD Operating Voltage Operating Current Standby Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Low Voltage Reset Voltage I/O Ports Sink Current REM Output Source Current Pull-high Resistance VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset 3/4 3V 3V 3V 3V 3/4 3V 3V 3V 3/4 3/4 Conditions 3/4 No load, fSYS=4MHz No load, system HALT 3/4 3/4 3/4 VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3/4 2.0 3/4 3/4 0 0.8VDD 1.8 4 -5 100 3/4 0.035 3/4 0.7 3/4 3/4 3/4 1.9 8 -7 150 3/4 3/4 3.6 1.5 1 0.2VDD VDD 2.0 3/4 3/4 200 100 3/4 Min. Typ. Max.
Ta=25C Unit V mA mA V V V mA mA kW mV V/ms
Rev.1.10
3
October 12, 2007
HT48RA0-3/HT48CA0-3
A.C. Characteristics
Symbol fSYS tSST tLVR tPOR Parameter System Clock System Start-up Timer Period Low Voltage Width to Reset Power-on Reset Low Pulse Width Test Conditions VDD 3V 3/4 3/4 3/4 Conditions fSYS=4MHz(3%) , Temp. = 0C ~ +50C Power-up, reset or wake-up from HALT 3/4 3/4 Min. 3880 3/4 0.25 1 Typ. 4000 1024 1 3/4 Max. 4120 3/4 2 3/4 Ta=25C Unit kHz tSYS ms ms
Note: tSYS=1/fSYS
Functional Description
Execution Flow The HT48RA0-3/HT48CA0-3 system clock is an RC type clock which requires the connection of an external resistor for its operation. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in program memory are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.
T1 T2 T3 T4 T1 T2 T3 T4
T1 S y s te m C lo c k
T2
T3
T4
In s tr u c tio n C y c le PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *9 0 *9 #9 S9 *8 0 *8 #8 S8 *7 0 @7 #7 S7 *6 0 @6 #6 S6 *5 0 @5 #5 S5 *4 0 @4 #4 S4 *3 0 @3 #3 S3 *2 0 @2 #2 S2 *1 0 @1 #1 S1 *0 0 @0 #0 S0
Mode Initial reset Skip Loading PCL Jump, call branch Return from subroutine
Program Counter + 2
Program Counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits Rev.1.10 4 S9~S0: Stack register bits @7~@0: PCL bits October 12, 2007
HT48RA0-3/HT48CA0-3
The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data and table and is organized into 102414 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
ble is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remaining 2 bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), where P indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory used to save the contents of the program counter only. The stack is organized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer and is neither readable nor writeable. At a subroutine call the contents of the program counter are pushed onto the stack. At the end of a subroutine signaled by a return instruction, RET, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost and only the most recent return address is stored. Data Memory - RAM The data memory is divided into two functional groups: special function registers and general purpose data memory (328). Most are read/write, but some are read only. The remaining space before the 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 3FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through memory pointer register (MP;01H).
This area is reserved for the initialization program. After a device reset, the program always begins execution at location 000H.
* Table location
Any location in the Program Memory space can be used as a look-up table. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory register, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the ta000H D e v ic e in itia liz a tio n p r o g r a m
n00H L o o k - u p ta b le ( 2 5 6 w o r d s ) nFFH P ro g ra m
3FFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 4 b its
Program Memory Table Location Instruction(s) *9 TABRDC [m] TABRDL [m] P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *9~*0: Table location bits P9~P8: Current program counter bits 5 @7~@0: Table pointer bits
Rev.1.10
October 12, 2007
HT48RA0-3/HT48CA0-3
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H G e n e ra l P u rp o s e D a ta M e m o ry (3 2 B y te s ) TSR0 TSR1 CARL0 CARL1 CARH0 CARH1 :U nused R e a d a s "0 0 " PB PA S p e c ia l P u r p o s e D a ta M e m o ry STATUS ACC PCL TBLP TBLH IA R MP
Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation to [00H] accesses the data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 7-bit register. Bit 7 of MP is undefined and reading will return the result 1. Any writing operation to MP will only transfer the lower 7-bits of data to MP. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. Data movement between two data memory locations has to pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions.
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the contents of the status register. Status Register - STATUS This 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Function
3FH
RAM Mapping
Bit No. 0
Label C
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
Rev.1.10
6
October 12, 2007
HT48RA0-3/HT48CA0-3
With the exception of the TO and PDF flags, the other status register bits can be altered by instructions like most other register. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, device power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Oscillator Configuration Only an external RC oscillator type is supported for the HT48RA0-3/HT48CA0-3.
OSC1 12kW
Watchdog Timer - WDT The WDT clock source is implemented by the instruction clock which is the system clock divided by 4. The clock source is processed by a frequency divider and a prescaler to provide various time out periods. WDT time out period = Clock Source 2n
Where n= 8~11 selected by a configuration option. The WDT timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation and the WDT will lose its protection purpose. In this situation the logic can only be restarted by external logic. A WDT overflow under normal operation will initialise a chip reset and set the status bit TO. To clear the contents of the WDT prescaler, two methods are adopted, software instructions or a HALT instruction. There are two types of software instructions. One type is the single instruction CLR WDT, the other type comprises two instructions, CLR WDT1 and CLR WDT2. Of these two types of instructions, only one can be active depending on the configuration option - CLR WDT times selection option. If the CLR WDT is selected (i.e.. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e.. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out.
RC
O s c illa to r
System Oscillator An external resistor between OSC1 and VSS in needed whose resistance must be 12kW for a 4MHz frequency. The RC oscillator provides 3% accuracy, the conditions are:
* VDD= 2.0V ~ 3.6V * Temperature = 0C ~ +50C * fSYS= 4MHz
C le a r W D T F r e q u e n c y D iv id e r C lo c k S o u r c e ( S y s te m C lo c k /4 ) 3 - b it C o u n te r P r e s c a lle r ( 8 - b it)
C o d e O p tio n S e le c t
C ode O p tio n
W DT T im e - o u t
C lo c k S o u r c e 2n
(n = 8 ~ 1 1 )
Watchdog Timer
Rev.1.10
7
October 12, 2007
HT48RA0-3/HT48CA0-3
Power Down Operation - HALT The Power-down mode is initialised by the HALT instruction and results in the following:
* The system oscillator turns off and the WDT stops. * The contents of the on-chip Data Memory and regis-
Some registers remain unchanged during reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 1 PDF 0 u u RESET Conditions Power-on reset during power-up LVR reset during normal operation WDT time-out during normal operation
ters remain unchanged.
* WDT prescaler is cleared. * All I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode by means of an external falling edge signal on port B. By examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when the system powers up or when a CLR WDT instruction is executed and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs during normal operation. The port B wake-up can be considered as a continuation of normal execution. Each bit in port B can be independently selected to wake up the device by the code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Once a wake-up event(s) occurs, it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur:
* Power On reset * Low Voltage reset * WDT time-out reset during normal operation
Note: u means unchanged. To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or when the system awakes from a HALT state. When a system power up occurs, an SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status is shown below. Program Counter WDT Prescaler Input/Output ports Stack Pointer Carrier output 000H Clear Input mode Points to the top of the stack Low level
HALT W DT LVR SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tio n C o ld R e s e t
OSC1
VDD
P o w e r-o n R e s e t
tR S S T T im e - o u t In te rn a l R e s e t
STD
Reset Configuration
Reset Timing Chart
Rev.1.10
8
October 12, 2007
HT48RA0-3/HT48CA0-3
The chip reset status of the registers is summarised in the following table: Register Program Counter MP ACC TBLP TBLH STATUS PA PB TSR0 TSR1 CARL0 CARL1 CARH0 CARH1 Note: u means unchanged x means unknown - stands for unimplemented Power On 000H -xxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx 1111 1111 1111 1111 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0010 Low Voltage Reset 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu 1111 1111 1111 1111 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0010 WDT Time-out (Normal Operation) 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu 1111 1111 1111 1111 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0010
Input/Output Ports There are an 8-bit bidirectional input/output port, a 6-bit input with 2-bit I/O port in the HT48RA0-3/HT48CA0-3, labeled PA and PB which are mapped to [12H], [14H] of the Data Memory, respectively. Each bit of PA can be selected as NMOS output or Schmitt trigger input with pull-high resistor by a software instruction. PB0~PB1 have the same structure as PA, while PB2~PB6 can only be used for input operation - Schmitt trigger with pull-high resistors. PB7 is used for input operation - Schmitt trigger but without pull-high resistor. When PA and PB are used for input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA and PB0~PB1 output operation, all data is latched and remains unchanged until the output latch is rewritten.
When PA and PB0~PB1 is used for input operation, it should be noted that before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is, the instruction SET [m].i (i=0~7 for PA, i=0~1 for PB) is executed first to disable related NMOS device, and then MOV A, [m] to get stable data. After chip reset, PA and PB remain at a high level input line. Each bit of PA and PB0~PB1 output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H or 14H) instructions respectively. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m], CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each line of PB has a wake-up capability selectable via a configuration option.
Rev.1.10
9
October 12, 2007
HT48RA0-3/HT48CA0-3
V
DD
D a ta b u s D W r ite C h ip R e s e t R e a d D a ta S y s te m W a k e -u p
Q CK S Q
W eak P u ll- u p PA0~PA7 PB0~PB1
C o d e O p tio n P B 0 ~ P B 1 o n ly
PA, PB0~PB1 Input/Output Lines
V
DD
P u ll- u p R e a d D a ta D a ta b u s S y s te m W a k e -u p C o d e O p tio n PB2~PB6
PB2~PB6 Input Lines
D a ta B u s R e a d D a ta S y s te m W a k e -u p C o d e O p tio n
PB7
PB7 Input Line
Timer The timer is an internal unit for creating a remote control transmission pattern. As shown, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. No. 0~7 Label t0~t7 Function Down counter
Timer Operation The timer starts counting down when a value other than 0 is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for making the timer start operation are shown below: MOV A,XXH MOV TSR0,A MOV A,XXH MOV TSR1,A SET TSR1.1 ; The timer is started by set t9=1 ; XX 01H, t8 TSR0 (18H) Register ; XX = 00H ~ FFH
No. 0 1 2~6 7
Label t8 t9 3/4 TOEF
Function Down counter Timer enable, initial value is 0. Unused bit, read as 0. Timer operation end flag, initial value is 1.
Addition notes for the 9-bit timer:
* Writing to TSR0 will only put the written data to the
TSR0 register (t7~t0) and writing to TSR1 (t8) will transfer the specified data and contents of TSR0 to the Down Counter. TOEF will be cleared after the data transferred from TSR1 and TSR0 to the Down Counter is completed and then wait until TSR1.1 is set by user.
* Setting TSR1.1=1, the timer will start counting. The
TSR1 (19H) Register
timer will stop when its count is equal to 0 and then TOEF is set equal to 1.
Rev.1.10
10
October 12, 2007
HT48RA0-3/HT48CA0-3
* If the TSR1.1 is cleared during the timer counting, the
In the case above, the timer output time is as follows. (Set value+1) 64/fSYS = (511+1) 16ms = 8.192ms
REM 8 .1 9 2 m s
timer will be stopped. Once the TSR1.1 is set (1(R)0(R)1), the down counter will reload data from t8~t0, and then the down counter begins counting down with the new load data.
* If TSR1.1 and TOEF are equal to 1 both, the timer can
re-start, after new data is written to TSR0, TSR1 (t0~t8) in sequence. Note: If the contents of the Down counter is 000H, set the t9 to start the timer counting, the timer will only count 1 step. The timer output time=64/fSYS. (R) [ (0+1) 64/fSYS=64/fSYS ]
The down counter is decremented (-1) in the cycle of 64/fSYS. If the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. At this time, TOEF will be set to 1. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. The following relational expression applies between the timers output time and the down counters set value. Timer output time = (Set value+1) 64/fSYS An example is shown below. MOV A,0FFH MOV TSR0,A MOV A,01H MOV TSR1,A SET TSR1.1
By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the REM pin. The REM pin can also output the carrier while the timer is in operation. Note: The carrier output results if bit 9 of the high-level period setting modulo register (CARH) is cleared (0).
REM
T im e r O u tp u t T im e : ( S e t v a lu e + 1 ) x 6 4 /fS
YS
Timer Output when Carrier is not Output
tS t9
R1
tS t8 t7 t6 t5 t4
R0
t3
t2
t1
t0 fS t9 /6 4
D o w n C o u n te r, (t8 ~ t0 )+ 1
Count C lo c k
YS
TOEF Z e ro D e te c to r C a r r ie r S y n c h ro n o u s C ir c u it REM C a r r ie r S ig n a l
Timer Configuration
Rev.1.10
11
October 12, 2007
HT48RA0-3/HT48CA0-3
Carrier Output
* Carrier output generator
The carrier generator consists of a 9-bit counter and two modulo registers for setting the high-level and low-level periods - CARH and CARL respectively. Register CARL0 CARL1 CARH0 CARH1 Bit7 CL.7 3/4 CH.7 3/4 Bit6 CL. 3/4 CH.6 3/4 Bit5 CL. 3/4 CH.5 3/4 Bit4 CL. 3/4 CH.4 3/4 Bit3 CL.3 3/4 CH.3 3/4 Bit2 CL.2 3/4 CH.2 3/4 Bit1 CL.1 Fix 0 CH.1 CH.9 (CARY) Bit0 CL.0 CL.8 CH.0 CH.8
CARL0 (1AH) Register, CARL1 (1BH), CARH0 (1CH) Register, CARH1 (1DH), Register Note: 1. CARH1.1 (CARY) initial value is 1. 2. CARL1.2 (CARH1.2)~CARL1.7 (CARH1.7) are unused bits, read as 0. The carrier duty ratio and carrier frequency can be determined by setting the high-level and low-level widths using the respective modulo registers. Each of these widths can be set in a range of 500ns to 64ms at fSYS = 4MHz. CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) are read and written using instructions. Example: MOV MOV MOV MOV MOV MOV MOV MOV CLR A,XXH CARL0,A A,XXH CARL1,A A,XXH CARH0,A A,XXH CARH1,A CARH1.1 ; The carrier is started by clearing CARY(CARH1.1)=0 ; XXH 02H, CH.8 (CARH1.0) ; XXH = 00H~FFH ; XXH 01H, CL.8 (CARL1.0) ; XXH = 00H~FFH
CARH CARH1 C a r r ie r S ig n a l C H .9 CARY C H .8 C H .7 C H .6 C H .5 CARH0 C H .4 C H .3 C H .2 C H .1 C H .0 CARL1 C L .9 (0 ) N o te 1 . C L .8 C L .7 C L .6
CARL CARL0 C L .5 C L .4 C L .3 C L .2 C L .1 C L .0
M o d u lo r e g is te r fo r s e ttin g th e h ig h - le v e l p e r io d (C A R H .8 ~ C A R H .0 )
M o d u lo r e g is te r fo r s e ttin g th e lo w - le v e l p e r io d (C A R L .8 ~ C A R L .0 )
S e le c to r
F /F
M a tc h
C o m p a ra to r
C le a r
9 - b it C o u n te r
fS
YS
t9 (N o te 2 ) fS
YS
Configuration of Remote Controller Carrier Generator Note: 1. Bit 9 of the modulo register for setting the low-level period (CARL) is fixed to 0. 2. t9: Flag that enables timer output (timer block, see Timer Configuration)
Rev.1.10
12
October 12, 2007
HT48RA0-3/HT48CA0-3
The values of CARH and CARL can be calculated from the following expressions. CARL (CARL1.0, CARL0.7~CARL0.0) = ( fSYS (1-D) T) - 1 CARH (CARH1.0, CARH0.7~CARH0.0) = ( fSYS D T) - 1 D: Carrier duty ratio (0 < D < 1) fSYS: Input clock (Mhz) T: Carrier cycle (ms) Ensure to input values in the range of 001H to 1FFH to CARL and CARH. Example: fSYS = 4MHz, fc = 38.1kHz, T = 1/ fc = 26.25ms, duty = 1/3 CARL = (4M (1-1/3) 26.25ms) - 1 = 69 = 45H CARH = (4M 1/3 26.25ms) - 1 = 34 = 22H MOV MOV MOV MOV CLR A,045H CARL0,A A,022H CARH0,A CARH1.1 ; The carrier is started by clearing CARY(CARH1.1) = 0
* Carrier output control
The remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register for setting the high-level period (CARH). When performing a carrier output, be sure to set the timer operation after setting the CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) values. Note that a malfunction may occur if the values of CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) are changed while the carrier is being output from the REM pin. Executing the timer manipulation instruction starts the carrier output from the low level.
T im e r O u tp u t T im e : ( S e t v a lu e + 1 ) x 6 4 /fS Y
S
T im e r O u tp u t
C a r r ie r tL tH
S e e N o te
Timer Output when Carrier Is an Output Note: When the carrier signal is active and during the time when the signal is high, if the timer output should go low, the carrier signal will first complete its high level period before going low.
Rev.1.10
13
October 12, 2007
HT48RA0-3/HT48CA0-3
The output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of CARH and the timer output enable flag (t9), and the value of the timer blocks 9-bit down counter (t0 to t8). CARH1.1 (CARY) 0 0 0 0 1 1 Timer Output Enable Flag (t9: TSR1.1) 0 0 1 1 0 1 9-bit Down Counter (TSR0.0~TSR0.7, TSR1.0) 0 Low-level output Other than 0 0 Other than 0 3/4 3/4 64/fsys (with carrier output) Carrier output (Note) Low-level output High-level output REM Pin
Note: Input values in the range of 001H to 1FFH to CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0). Caution: CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) must be set while the REM pin is low level (t9 = 0 or t0 to t8 = 0). CARH (CARH1.0, CARH0.7~CARH0.0) 01H 03H 09H 13H 20H 21H 22H 22H 22H 23H 24H 34H 3BH 63H 7FH CARL (CARL1.0, CARL0.7~CARL0.0) 01H 05H 09H 13H 20H 41H 44H 45H 46H 48H 49H 6AH 3BH 63H 7FH
tH (ms) 0.5 1.0 2.5 5.0 8.25 8.25 8.75 8.75 8.8 9.0 9.26 13.33 15.0 25.0 32.0
tL (ms) 0.5 1.5 2.5 5.0 8.25 16.75 17.25 17.5 17.6 18.25 18.52 26.66 15.0 25.0 32.0
t (ms) 1.0 2.5 5.0 10.0 16.5 25 26.0 26.25 26.4 27.25 27.78 40.0 30.0 50.0 64.0
fC (kHz) 1000 400 200 100 60.6 40 38.5 38.10 37.9 36.7 36.0 25 33.3 20 15.6
Duty 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/2 1/2 1/2
Carrier Frequency Setting (fSYS=4MHz)
tL tH C a r r ie r S ig n a l t
Rev.1.10
14
October 12, 2007
HT48RA0-3/HT48CA0-3
Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
V 1 .9 V
* The low voltage (0.9V~VLVR) has to remain in this
The relationship between VDD and VLVR is shown below.
VDD 3 .6 V
LVR
state for a time in excess of 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
0 .9 V
V 3 .6 V
DD
V
LVR
L V R D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1 To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before entering normal operation. *2 Since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters the reset mode.
Configuration Options The following table shows eight kinds of configuration options for the HT48RA0-3/HT48CA0-3. All the configuration options must be defined to ensure proper system functioning. No. 1 2 3 Code Option WDT time-out period selection 2n , where n=8~11. Time-out period= Clock Source WDT enable/disable selection. This option is to decide whether the WDT timer is enabled or disabled. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, the WDT can be cleared. Wake-up selection. This option defines the wake-up activity function. External input pins (PB only) all have the capability to wake-up the device. LVR function: enable or disable
4 5
Rev.1.10
15
October 12, 2007
HT48RA0-3/HT48CA0-3
Application Circuits
PA0~PA7 OSC C ir c u it OSC1 PB0~PB1 PB2~PB7 REM H T 4 8 R A 0 -3 /H T 4 8 C A 0 -3 R V
DD
470pF
OSC
OSC1
R C S y s te m R OSC=12kW
O s c illa to r
OSC
C ir c u it
Example
PB1 PB0 PA3 PA2 PA1 PA0 33W 1W Vbat 220W ~1kW 100mF VDD
PB2 PB3 PB4 PB5 PB6 PB7 PA7 PA6 PA5
REM
PA4
OSC C ir c u it
OSC1
H T 4 8 R A 0 -3 /H T 4 8 C A 0 -3
Rev.1.10
16
October 12, 2007
HT48RA0-3/HT48CA0-3
Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Rev.1.10
17
October 12, 2007
HT48RA0-3/HT48CA0-3
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
Rev.1.10
18
October 12, 2007
HT48RA0-3/HT48CA0-3
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev.1.10
19
October 12, 2007
HT48RA0-3/HT48CA0-3
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev.1.10 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 20 October 12, 2007
HT48RA0-3/HT48CA0-3
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev.1.10
21
October 12, 2007
HT48RA0-3/HT48CA0-3
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
Rev.1.10
22
October 12, 2007
HT48RA0-3/HT48CA0-3
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev.1.10
23
October 12, 2007
HT48RA0-3/HT48CA0-3
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
Rev.1.10
24
October 12, 2007
HT48RA0-3/HT48CA0-3
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev.1.10
25
October 12, 2007
HT48RA0-3/HT48CA0-3
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev.1.10
26
October 12, 2007
HT48RA0-3/HT48CA0-3
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev.1.10
27
October 12, 2007
HT48RA0-3/HT48CA0-3
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev.1.10
28
October 12, 2007
HT48RA0-3/HT48CA0-3
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev.1.10
29
October 12, 2007
HT48RA0-3/HT48CA0-3
Package Information
20-pin SOP (300mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 490 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 510 104 3/4 3/4 38 12 10
Rev.1.10
30
October 12, 2007
HT48RA0-3/HT48CA0-3
20-pin SSOP (150mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 150 8 335 49 3/4 4 15 7 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 244 158 12 347 65 3/4 10 50 10 8
Rev.1.10
31
October 12, 2007
HT48RA0-3/HT48CA0-3
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 20W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
SSOP 20S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 16.8+0.3 -0.2 22.20.2
Rev.1.10
32
October 12, 2007
HT48RA0-3/HT48CA0-3
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0+0.3 -0.1 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.80.1 13.30.1 3.20.1 0.30.05 21.3
SSOP 20S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0+0.3 -0.1 8.00.1 1.750.1 7.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 6.50.1 9.00.1 2.30.1 0.300.05 13.3
Rev.1.10
33
October 12, 2007
HT48RA0-3/HT48CA0-3
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev.1.10
34
October 12, 2007

▲Up To Search▲

Price & Availability of HA0041E

	To Download HA0041E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .